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Memory Subsystem Design Engineer, Platforms

Company: Google Inc.
Location: Sunnyvale
Posted on: June 10, 2021

Job Description:

Minimum qualifications:

  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent in practical experience.
  • 6 years of industrial experience (or equivalent practical experience).
  • Experience in logic design, microarchitecture, specification, SystemVerilog RTL design, functional verification, and power, performance, or area optimization.
  • Experience designing control and interface logic for memory technologies (i.e. DDR, HBM, GDDR, etc.).

Preferred qualifications:

  • PhD degree in Electrical Engineering, Computer Engineering, or Computer Science.
  • 7 years of experience in ASIC design.
  • Experience applying engineering best practices (e.g. code review, testing, refactoring).
  • Experience in one or more successful ASIC products from concept to silicon.
  • Deep understanding in computer architecture / memory subsystem architecture.
  • Knowledge of machine learning, video processing, or SoC design.

About the job

Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.

With your technical expertise, you lead projects in multiple areas of expertise (i.e., engineering domains or systems) within a data center facility, including construction and equipment installation/troubleshooting/debugging with vendors.

As a memory subsystem design engineer within the Chip Implementation and Infrastructure Engineering IO subsystem team you will participate in the architecture and implementation of custom ASIC designs critical to Google's mission. Our hardware is used to accelerate and serve workloads essential to Google's users. You'll see the impact of your work in the Google products you enjoy each day. You'll use your passion and background for elegant hardware design to develop state-of-the-art custom memory interface logic to create products that are making a real difference.

Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.

Responsibilities

  • Define architecture / micro-architecture specifications for memory-related (e.g. DDR, HBM) subsystems including memory controllers and interconnect logic.
  • Take ownership of one or more modules and implement RTL.
  • Converge functionality and PPA of the design and create simple test benches.
  • Work closely with software teams to ensure end to end solutions.
  • Contribute to design methodology, libraries and code review.

Keywords: Google Inc., Sunnyvale , Memory Subsystem Design Engineer, Platforms, Other , Sunnyvale, California

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