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Architecture and Design Engineer, ML Accelerator ASIC, Platforms

Company: Google
Location: Sunnyvale
Posted on: January 12, 2021

Job Description:

About the job Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.You will be part of a team developing cutting-edge ASICs used to accelerate computation in data centers. You will have dynamic, multi-faceted responsibilities in areas such as project definition, design, and implementation. You will participate in the design, architecture, documentation, and implementation of the next generation of data center accelerators.Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible. Responsibilities Understand the overall application of the chip, proposing and developing improvements in mathematical components based on new applications or research, as well as in overall design.Design and document one or more blocks of an ASIC, including functionality and timing, while applying engineering best practices.Implement your designs in RTL (System Verilog or other HDLs) and iterate the design for optimal power, timing, and area.Create simple test benches and debug complex logic simulations.Work closely with compiler and software teams on functionality, interfaces, and documentation. Qualifications Minimum qualifications:Master's degree in Electrical Engineer or Computer Science or equivalent practical experience.5 years of industrial experience in applying computer architecture principles to solve open-ended problems.Experience with arithmetic units architecture and number representation.Experience in RTL design and logic synthesis, verification, timing closure and physical design principles.Preferred qualifications:PhD degree in Electrical Engineer or Computer Science or equivalent practical experience.5 years of experience in FPGA/ASIC design and experience with ASIC development.Experience with computer arithmetic and analyzing power/performance/area trade-offs for ALU (arithmetic logic unit) components.Experience with modeling mathematical components.Experience with highly pipelined designs, and with multiple-clock-domain designs.Knowledge of machine learning algorithms, processor design, accelerators, and/or memory hierarchies.

Keywords: Google, Sunnyvale , Architecture and Design Engineer, ML Accelerator ASIC, Platforms, Other , Sunnyvale, California

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