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Architecture and System Integration Technical Lead, Accelerator ASIC

Company: Google
Location: Sunnyvale
Posted on: March 20, 2023

Job Description:

Architecture and System Integration Technical Lead, Accelerator ASIC

  • Master's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
  • 8 years of experience in architecture, hardware and software co-design.
  • 5 years of experience in Verilog/SystemVerilog or C/C++ development.
  • Experience bringing up hardware functionality through Simulations/FPGAs/Emulation and ASIC/FPGA architecture, or compiler design.
    Preferred qualifications:
    • PhD in Electrical Engineering, Computer Engineering, Computer Science or related fields.
    • Experience writing production software or validation tests in C++ and testing.
    • Experience planning and delivering chip bringup with hardware and software co-design and integration.
      About the jobThe Silicon Validation and Prototyping team is responsible for the development, bringup and qualification, deployment, and sustaining quality of our custom silicon. We integrate complex hardware and software stacks and operate them on emulation platforms for pre-silicon validation. We create software-based custom test cases, workloads, test generators, infrastructure, analysis tools, and debugging tools. In later phases, we are responsible for silicon bringup, validation, characterization and qualification, and sustaining programs and their quality. We help ensure our fleet runs at maximum efficiency, and when problems arise we help debug and root cause those issues.
      Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.Additional Information:The US base salary range for this full-time position is $172,000-$263,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target for new hire salaries for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

      Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.
      • Own end-to-end functionality of chip features through compiler, firmware and driver stack.
      • Bringup chip features/subsystems on software models and hardware prototypes (e.g., Emulation/FPGA).
      • Develop the integration plan with software and system partners. Coordinate hardware and software delivery and benchmark performance.
      • Plan and design validation tests and microbenchmarks to validate chip functionality and performance.
      • Provide metrics and feedback to Architecture and Design teams to improve chip performance, efficiency, usability, power management, quality, and reliability.Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a need that requires accommodation, please let us know by completing our Accommodations for Applicants form .To all recruitment agencies: Google does not accept agency resumes. Please do not forward resumes to our jobs alias, Google employees or any other organization location. Google is not responsible for any fees related to unsolicited resumes.At Google, we're committed to building a workforce that is more representative of the users we serve and creating a culture where everyone feels like they belong. To learn more about our diversity, equity, inclusion commitments and how we're building belonging, please visit our Belonging page for more information.We welcome and encourage people who are expecting and/or parents-to-be to apply to this or any other role at Google.Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles.

Keywords: Google, Sunnyvale , Architecture and System Integration Technical Lead, Accelerator ASIC, IT / Software / Systems , Sunnyvale, California

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