R&D Sr Staff Software Engineer - Mixed Signal Verification (C/C++)
Company: Synopsys Inc
Posted on: May 10, 2022
This position is a senior staff engineer at Synopsys which has
product ownership and will play a leadership role to develop and
support the next generation of mixed-signal verification (MSV)
tools. You will be joining a world class team for EDA product
development to serve the growing semiconductor industry. The ideal
candidate should have strong desires to learn and explore new
technologies and demonstrates good analysis and problem-solving
skills. Prior knowledge and experience of EDA tool development are
required. The MSV solution development typically needs knowledge
from different areas (digital Verilog simulator, analogSPICE
simulator and GUI environment). The position will also need to work
with Application Engineers to support customers (bug fix and
feature enhancement). Responsibilities: Responsible for designing,
developing, troubleshooting, or debugging software programs.
Strengthen the current VAMS simulation flow by enhancing its
features in connect module customization, UPF power annotation.
Integrate the MSV flow into design/debug environment. Develop
post-layout flow to handle SPF and SDF for MSV. Support MSV
customer engagement and fulfill customers--- requirements. Develop
MSV solution for AMS regression (SV assertion and UVM-Universal
Verification Methodology). Work with AE to define projects, collect
requirements, write up specification, implement and then test the
software. Work is self-directed and collaborative in nature.
Frequently networks with senior internal and external personnel in
their own area of expertise. Requirements: MS/Ph.D. degree with 10
years of related large-scale EDA software development experience.
Knowledge of SPICE simulation Verilog, System-Verilog and
Verilog-AMS language is required. Expertise in the development of
complex software projects with C/C++ coding in a Linux environment.
Proven background in data structures and algorithm development.
Experience of executing white box testing, code review, code
coverage and assertion. Knowledge of post-layout back annotation
with SPF and SDF is a plus. Knowledge of UPF, UVM(Universal
Verification Methodology) and SVA (System-Verilog Assertion) is a
plus. Synopsys tools (VCS, Primesim, Finesim, XA and Custom
Compiler) is desired. Project leading skills to initiate
cross-organizational projects Autonomously resolves a wide range of
issues in imaginative ways on a regular basis. The Custom Design
and Manufacturing Group provides market leading solutions for
Custom Design, Circuit Simulation, Physical Verification, Process
Technology Development, Advanced Lithography, and Manufacturing,
driving the successful adoption of our best-in-class technologies
and platforms at our broad and growing set of customers and
partners across diverse market segments. At Synopsys, we---re at
the heart of the innovations that change the way we work and play.
Self-driving cars. Artificial Intelligence. The cloud. 5G. The
Internet of Things. These breakthroughs are ushering in the Era of
Smart Everything. And we---re powering it all with the world---s
most advanced technologies for chip design and software security.
If you share our passion for innovation, we want to meet you.
Inclusion and Diversity are important to us. Synopsys considers all
applicants for employment without regard to race, color, religion,
national origin, gender, sexual orientation, gender identity, age,
military veteran status, or disability.
Keywords: Synopsys Inc, Sunnyvale , R&D Sr Staff Software Engineer - Mixed Signal Verification (C/C++), IT / Software / Systems , Sunnyvale, California
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