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ASIC Design Engineer

Company: Theery
Location: Sunnyvale
Posted on: November 10, 2019

Job Description:

As the ASIC / RTL / FPGADesign Lead you will work on the next generation ASIC style IP development for high speed IO interfaces. The successful candidate will be primarily responsible for activities covering the whole ASIC frontend flow, which includes developing micro-architecture specifications, implementing the RTL code, upper level integration, synthesizing and optimizing the design for better timing, area and power, inserting DFT scan chain, doing performance analysis, setting up block level test bench, carrying on the verification tasks and analyzing the coverage results. You will also be responsible for interfacing with the backend team on STA, timing closure and P&R, and participating in silicon bring up. You will be working and interacting with both digital and analog circuit designers.
The successful candidate's will have:

  • BSEE or equivalent with a minimum of 5+ years of ASIC design experiences is required.
  • Experience in high speed and low power digital design using advanced deep micron process.
  • Proficient with Verilog coding skills and familiar with programming script such as Perl, Tcl or Python is required.
  • Familiar with Design Compiler or DCT and PrimeTime is required.
  • Strong communication and written skills and a good team player is required.

Keywords: Theery, Sunnyvale , ASIC Design Engineer, Engineering , Sunnyvale, California

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