Synthesis & Timing Engineer
Posted on: February 12, 2024
Posted: Feb 3, 2024
Come and join Apple's growing wireless silicon development team.
Our Wireless SoC organization is responsible for all aspects of
wireless silicon development, emphasizing highly energy-efficient
design and new technologies that transform the user experience at
the product level. This is driven by a world-class vertically
integrated engineering team spanning RF/Analog architecture and
design, Systems/PHY/MAC architecture and design, VLSI/RTL design
and integration, Emulation, Design Verification, Test and
Validation, and FW/SW engineering. We encourage you to apply if you
enjoy a fast-paced and exciting environment, collaborate with
people across different functional areas, and thrive during
- BS and 3+ years of relevant industry experience.
- Knowledge of the ASIC design flow, synthesis, static timing
analysis, scripting, and netlist generation.
- Expertise in STA tools and flow.
- UPF usage for power and voltage islands.
- Logic synthesis execution for efficient PPA using physically
aware techniques in single-digit process nodes using Design
Compiler, Fusion Compiler &/or Genus.
- Hands-on experience in timing/SDC constraints generation and
- Knowledge of timing corners, operating modes, process
variations, and signal integrity-related issues.
- Proficient in scripting languages (Tcl and Perl).
- Proficient in the closure of end-to-end logic equivalence (FV,
LEC) with functional ECOs in the mix.
- Familiarity with DFT and backend related methodology and
- Proficient with RTL Verilog/VHDL.
- Familiarity with digital top integration
- Experience with script-based tool automation and familiarity
with API's and scripting languages for design tools, such as;
Design Compiler, Genus, PrimeTime, etc. is a plus.
As a Timing Engineer, you will work in a team developing Wireless
SoCs with custom hardware accelerators and multiple ARM-based
sub-systems. Have the opportunity to work closely with SoC
architects and IP developers to develop SoCs that meet Apple
devices' power, performance, and area goals. You will help define
the processes, methods, and tools for designing and implementing
these large, complex SoCs. Collaboration with multi-disciplinary
groups will be needed to make sure designs are delivered on time
and with the highest quality by incorporating accurate checks at
every stage of the design process. In this highly visible role, you
will be at the center of the ASIC creation effort, interfacing with
all disciplines, with a critical impact on getting leading-edge
products out to delight millions of customers. - Full chip and
block-level timing constraint and closure ownership throughout the
entire project cycle (RTL, synthesis, and physical implementation).
- Execute low power design and physical synthesis techniques,
deploying knowledge of UPF and power intent verification. - Deploy
and enhance methodology and flows related to timing constraint
verification and timing closure. - Generation of consistent block
and full chip timing constraints. - Support digital chip
integration work and flows. - Collaborate with Chip Architecture,
Design Verification, Physical Design, DFT, and power teams to
achieve the first tape out success on designs - generally bridging
the RTL and place & route worlds.
Education & Experience
Education & Experience
BS and 3+ years of relevant industry experience.
- Apple is an equal opportunity employer that is committed to
inclusion and diversity. We also take affirmative action to offer
employment and advancement opportunities to all applicants,
including minorities, women, protected veterans, and individuals
with disabilities. Apple will not discriminate or retaliate against
applicants who inquire about, disclose, or discuss their
compensation or that of other applicants.
Pay & Benefits
Pay & Benefits
- At Apple, base pay is one part of our total compensation
package and is determined within a range. This provides the
opportunity to progress as you grow and develop within a role. The
base pay range for this role is between $138,900.00 and
$256,500.00, and your base pay will depend on your skills,
qualifications, experience, and location.
Apple employees also have the opportunity to become an Apple
shareholder through participation in Apple's discretionary employee
stock programs. Apple employees are eligible for discretionary
restricted stock unit awards, and can purchase Apple stock at a
discount if voluntarily participating in Apple's Employee Stock
Purchase Plan. You'll also receive benefits including:
Comprehensive medical and dental coverage, retirement benefits, a
range of discounted products and free services, and for formal
education related to advancing your career at Apple, reimbursement
for certain educational expenses - including tuition. Additionally,
this role might be eligible for discretionary bonuses or commission
payments as well as relocation. Learn more about Apple
Note: Apple benefit, compensation and employee stock programs are
subject to eligibility requirements and other terms of the
applicable plan or program.
Apple is an equal opportunity employer that is committed to
inclusion and diversity. We take affirmative action to ensure equal
opportunity for all applicants without regard to race, color,
religion, sex, sexual orientation, gender identity, national
origin, disability, Veteran status, or other legally protected
Keywords: Apple, Sunnyvale , Synthesis & Timing Engineer, Engineering , Sunnyvale, California
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