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Senior ASIC Design Engineer

Company: Sql Pager LLC
Location: Sunnyvale
Posted on: June 21, 2022

Job Description:

Responsibilities:

  • To help develop an ASIC for our automotive and Data Center artificial intelligence computing architecture
  • Participating in Architecture definition and modeling, verification test plan and testbench
  • Developing the micro-architecture specification, RTL in Verilog/System Verilog, performance/speed/power goals.
  • Bring up the chip in lab, composing bring-up scripts.
  • Collaborate with verification, software and system teams to ensure a successful product deliveryRequired Skills:
    • MS with 10+ years or PhD with 8+ years, 5+ years in ASIC design team lead
    • Experience in logic design on high-performance data center chip and integration of acquired IP blocks
    • Good knowledge on ASIC design and verification methodologies and flows
    • Hand-on experience: System Verilog, C++, Perl/Python, UVM, Synthesis, Formal Verification, Static Timing Analysis
    • Experience with processor design, AI/Deep Learning, PCIe/DDR, FPGA emulation
    • Proven track record as ASIC design on several production tape-outs
    • Excellent written and verbal interpersonal skills

Keywords: Sql Pager LLC, Sunnyvale , Senior ASIC Design Engineer, Engineering , Sunnyvale, California

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