Design Verification Engineer
Company: Synchrony Systems, Inc
Posted on: June 20, 2022
- 1, 2 years of experience in UVM or graduate certificate in ASIC
- Defined verification methodology using UVM/SystemVerilog.
- Verification based on architectural/micro-architectural
specification review and analysis. Implemented testbench and
- Hands on experience on block level, gate level, and chip level
- Understanding of different RTL design and verification
- 2, 3 projects with coverage closure + tests debug.
- Able to maintain scripts written in Python, Perl, BashThanks &
Regards Ajeet Kumar Sr. Technical Recruiter US Direct: 469-813-9539
Email: firstname.lastname@example.org - URL:
Keywords: Synchrony Systems, Inc, Sunnyvale , Design Verification Engineer, Engineering , Sunnyvale, California
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