Design Verification Engineer

Company: Synchrony Systems, Inc
Location: Sunnyvale
Posted on: June 20, 2022

Job Description:

Job Description:

1, 2 years of experience in UVM or graduate certificate in ASIC Design Verification.
Defined verification methodology using UVM/SystemVerilog.
Verification based on architectural/micro-architectural specification review and analysis. Implemented testbench and verification components.
Hands on experience on block level, gate level, and chip level verification
Understanding of different RTL design and verification strategies
- Desirable:
- 2, 3 projects with coverage closure + tests debug.
- Able to maintain scripts written in Python, Perl, BashThanks & Regards Ajeet Kumar Sr. Technical Recruiter US Direct: 469-813-9539 Email: ajeet@synchronycorp.com - URL: http://www.synchronycorp.com

Keywords: Synchrony Systems, Inc, Sunnyvale , Design Verification Engineer, Engineering , Sunnyvale, California

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