Silicon Design Verification Engineer

Company: Ursus
Location: Sunnyvale
Posted on: January 11, 2022

Job Description:

Job Title: Silicon Design Verification EngineerLocation: Sunnyvale, CADuration: 1 YearSummary:Power and performance modeling or DV (C, system C, system Verilog, or matlab)Strong DV background (test plan development, test writing, UVM)Experience with low power verification (UPF)Experience with both static (i.e. VC LP) and dynamic (i.e. VCS NLP) power-aware verification flowsDuties:Responsible for low power verification including both dynamic and static verificationWrite and augment existing testplans.Implement testbench and scoreboards / checkers.Implement test sequences as per plan and debug failuresAchieve 100% functional, code, and power coverageWork closely with designers, micro architects & f/w to resolve issuesAbility to communicate & articulate clearly progress / issues with project leadsMust Have:7+ years of proven experience as a DV engineerImplied: Candidate will have hands on Experience with executable test plans and Coverage Driven verificationHands on experience with SV (SystemVerilog) and UVM (Universal Verification Methodology)Hands on Experience with Synopsys VCS / Verdi or Cadence Incisive toolsExperience with UPF based simulation flow2+ Years of experience with C/C++Nice to Have:Power and performance FPGA validationHifi4, TIE, CNN, DSP, fixed point, floating point, SONICS, python.Experience with Power Aware GLS flowTcl and Python (or similar) scripting languageASIC design experienceExperience in formal property verification of complex compute blocks like DSP, CPU or HW acceleratorsExperience with complex SoCsKnowledge of coverage merging across simulation and formalMSEE/CS or equivalent experienceEducationMust Have: Bachelor degree in Electrical/Computer Engineering or Computer ScienceMaster's Degree preferred but not requiredIND123

Keywords: Ursus, Sunnyvale , Silicon Design Verification Engineer, Engineering , Sunnyvale, California