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Verification Engineer

Company: Collabera Inc.
Location: Sunnyvale
Posted on: January 9, 2022

Job Description:

  • The main function of the Verification Engineer is to work with a group of engineers to own the design system level verification of our products.
  • Working closely with researchers, architects, and designers in architecting methods of design verification for multiple state of the art systems.
  • Using design verification skills to define verification requirements, create test cases, design and implement the testing infrastructure, execute the testing, and report the results for the new product designs. Job Responsibilities: Responsible for Design verification:
    • Implement testbench and scoreboards / checkers.
    • Implement test sequences as per plan and debug failures.
    • Achieve 100% functional, code, and power coverage.
    • Write and augment existing testplans.
    • Keep track of coverage metrics and bugs encountered and fixed.
    • Own execution, interpretation, and reporting of verification work status and results.
    • Support system bring up and debug activities.
    • Work closely with designers, micro architects & f/w to resolve issues.
    • Clearly communicate & articulate clearly progress / issues with project leads. Skills:
      • 7+ years of proven experience as a DV engineer
      • Hands on Experience with executable test plans and Coverage Driven verification
      • Hands on experience with SV (SystemVerilog) and UVM (Universal Verification Methodology)
      • Hands on Experience with Synopsys VCS / Verdi or Cadence Incisive tools Nice to have:
        • Experience with UPF and Power Aware GLS flow
        • TCL and Python (or similar) scripting language
        • Power and performance modeling or DV (C, system C, system Verilog, or MATLAB)
        • Power and performance FPGA validation
        • Hifi4, DSP, TIE, CNN, DSP, fixed point, floating point, SONICS, python
        • Experience with firmware verification
        • Experience with board level verification Education/Experience:
          • Preferred MSEE/CS or equivalent experience
          • Required BSEE/CS or equivalent experience
          • We are looking for candidates who has hands on experience with the System VeriLog and UVM and some level of understanding on the C-programming. Any exposure to FPGA or Silicon bring up is plus.
          • Coding and scripting skills
          • Candidates must have SV and UVM experience

Keywords: Collabera Inc., Sunnyvale , Verification Engineer, Engineering , Sunnyvale, California

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