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Design Verification Engineer

Company: Radiansys Inc.
Location: Sunnyvale
Posted on: January 18, 2020

Job Description:

Please find the job description anyone interested can share your resume at pkumar@radiansys.com Job Title: Design Verification EngineerLocation: Sunnyvale, CAFull Time----Develop a block-level test plan, UVM test bench components such as agents(drivers/monitors), scoreboard, constrained random test cases based on UVM sequences, assertions. Develop and close functional coverage, code coverage. Ability to independently execute on test plan, run simulations and debug.----Required:--7+ years of ASIC verification experience--UVM/System Verilog----VCS simulator, Verdi--2, 3 projects experience with UVM based testbench, coverage closure--Previous experience with PCIe, Ethernet, HBM-DDR, Processor verification, floating-point computational unit highly desired--C/C++ experience is desired--Scripting--skills(Perl, Python)--Formal verification experience is a plus--Regards,------------Pinku Kumar----Talent Acquisition - Radiansys Inc.----39510 Paseo Padre Pkwy #110, Fremont, CA 94538------------Direct: 510 790 2000 Ext 1006 Email:--pkumar@radiansys.com

Keywords: Radiansys Inc., Sunnyvale , Design Verification Engineer, Engineering , Sunnyvale, California

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