Design Automation DevOps Technical Lead Manager
Company: Intel GmbH
Location: Santa Clara
Posted on: May 9, 2024
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Job Description:
Job DescriptionAbout the GroupAs the world's largest chip
manufacturer, Intel strives to make every facet of semiconductor
manufacturing state-of-the-art -- from semiconductor process
development and manufacturing, through yield improvement to
packaging, final test and optimization, and world class Supply
Chain and facilities support. Employees in the Technology
Development and Manufacturing Group are part of a worldwide network
of design, development, manufacturing, and assembly/test
facilities, all focused on utilizing the power of Moore's Law to
bring smart, connected devices to every person on Earth.Foundry
Technology Development (TD) is the heart and soul of Moore's Law at
Intel. TD has enabled Intel to create world-changing technology
that enriches the lives of every person on earth. TD's more than
10,000 employees drive breakthrough research, develop next
generation process and packaging technologies, while also running
high volume manufacturing operations in its state-of-the-art
facilities in Oregon and Arizona. You will be a key member of the
Design Enablement customer application and support team and will
own significant customer enablement tasks in a fast-paced and
technically challenging environment. TD is working on development
of the best-in-class technology platform for the Foundry customers.
Our organization is responsible for enabling the FIP segment of the
platform, focusing on embedded custom memories, memory compilers,
standard cell libraries and analog and mixed signal foundational
IPs. As a technical leader in the Foundational IP (FIP) Enablement
and Support team, you will be responsible for building, evolving
and managing the Design Automation DevOps functions while leading
and developing management skills or managers with relevant hands-on
experience.We are looking to establish crucial development and
deployment capabilities for our team in:- Cross-platform QA and
delivery of applications improving FIP ease of use and
customization.- Integration QA workflows verifying compatibility
with multiple EDA reference workflows in the SoC design context.-
Streamlining of the FIP platform specification development and
change control, and QA integration.- Support and development
process integration in tools like GitHub, Jira Software and Jira
Service Management.You will be responsible for but not limited to:-
Architecting design automation solution, contributing to
implementation, leveraging industry standard DevOps tools and
methods for CI/CD and applications delivery.- Collaborate with the
org leadership and Technical Program Management on the design
automation roadmap definition, prioritization, effort and
scheduling estimates.- Apply your leadership experience to coach
and upskill design automation team members and collaborate closely
with SoC design and IP QA experts on streamlining and scaling of
the FIP Integration QA solutions.#Design
EnablementQualificationsYou must possess the below minimum
qualifications to be initially considered for this position.
Preferred qualifications are in addition to the requirements and
are considered a plus factor in identifying top candidates.Minimum
Qualifications:Candidate will possess a BS degree with 6+ years of
experience or MS degree with 4+ years of experience or PhD degree
with 2+ years of experience in Electrical Engineer or Computer
Engineering or related STEM field.In addition to minimum degree and
experience, you will have 8+ years of relevant experience in:
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Keywords: Intel GmbH, Sunnyvale , Design Automation DevOps Technical Lead Manager, IT / Software / Systems , Santa Clara, California
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